The Freescale PowerQuicII Pro 8313 RDB Board with Linux and Codewarrior IDE

By JB, MSEE

 

(rev 1.1)

Contents

Introduction. 1

Board Hardware Features. 2

An Example 8313 Application: Printer CPU.. 5

The Freescale 8313 PowerPC. 5

Codewarrior for 8313 RDB. 7

UBOOT and the Freescale Linux Board Support Package. 8

Compiling and downloading 8313 RDB Software. 9

8313RDB Configuration File Contents. 9

 

Introduction

 

This tech note page describes the Motorola 8313 RDB board with Linux RTOS in flash.
It describes the board features, how to use UBOOT to launch Linux, and how to download and execute software written using the Codewarrior IDE.

Motorola describes the 8313 processor as follows:

“The MPC8313E communications processor family meets the requirements of several small office/home office (SOHO), printing, IP services and industrial control applications.”

 

 

100_2469

Freescale 8313 RDB Board with 8313 processor

 

Board Hardware Features

 

The lists below were reproduced from Motorola’s specs, with the authors comments.

Processor:

* Freescale MPC8313E running at 333/333 MHz (CPU/DDR2)  - DDR2 memories are capable of speeds to about 400MHz. Data is clocked on each edge.

 

Memory:

* 128 MByte unbuffered DDR2 SDRAM discrete devices – close proximity to memory controller.

* 8 MByte Flash single-chip memory

* 32 MByte NAND Flash memory

* 256 KBit M24256 serial EEPROM

* SD connector to interface with the SD memory card in SPI mode  - SPI interfaces include clock, input, and output; data can be clocked in and out simultaneously.

 

Interfaces:

* 10/100/1000 BaseT Ethernet ports: (Two external interface modes. The RGMII interface is used with an external switch to support five Ethernet ports.

o 8313 eTSEC1, RGMII interface: five 10/100/1000 BaseT RJ-45 interfaces using Vitesse™ VSC7385 L2 switch

o 8313 eTSEC2, selectable RGMII or SGMII interface: one 10/100/1000 BaseT RJ-45 interface using Mavell™ 88E1111 PHY

* USB 2.0 port: (On chip or off chip PHY hardware.)

o High speed host/device USB interface: selectable on-chip PHY or external ULPI PHY interface by SMSC USB3300 USB PHY

* PCI: 32-bit PCI interface running at up to 66 MHz (PCI is a PCISIG standard)

o One 32-bit 3.3 V PCI slot connected to PCI bus

o One 32-bit 3.3 V miniPCI slot connected to PCI bus

* Dual UART ports:

o DUART interface: supports two UART up to 115200bps for console display – Can be displayed using PC serial port and hyperterminal.

 

Board connectors:

* LCD connectors by GPIO

* ATX power supply connector – 5V input only.

* JTAG/COP for debugging – uses Codewarrior USB Tap interface

 

 

100_2468

Freescale 8313 RDB Board with 8313 processor

 

 

Board Block Diagram

MPC8313ERDB_BD

(reproduced from Freescale website)

 

An Example 8313 Application: Printer CPU

 

The 8313 can be used as a network or USB printer CPU. User data to be printed can be manipulated in RAM, and printer imaging controls can be accessed via a local bus interface to an ASIC or FPGA with interface logic.

A simple text LCD can be controlled via the GPIO interface.

An external Ethernet PHY module can be used to interface the printer to a network, if required. One of the built-in USB interfaces can be used to wake up the printer upon activity.

 

The Freescale 8313 PowerPC

 

The 8313 RDB contains a PowerQuicII core. An 8313 block diagram is reproduced below.

 

 

MPC8313E Block Diagram

MPC8313EPR_BLKDIAG

 

 

The e300 core has an L1 16K instruction cache and a separate L1 16K data cache.

The e300 Core power is approximately 1.2W. Standby power is less than 300mW.

PowerQuicII pro devices such as the 8313E include a security feature module.

The processor can boot from NOR or NAND devices and includes one SPI interface and two I2C interfaces.

The IC circuits include 4 DMA controllers that support I/O, and a built-in programmable interrupt controller.

 

Codewarrior for 8313 RDB

 

The Codewarrior RDB includes a project creation wizard that allows one to automatically include libraries with drivers for devices on the 8313RDB. Users can select C or C++ code.

 

Freescale provides source code modules that can be edited for re-use, including main.cpp, interrupt.c, and sc_handler.c (a system call handler).

 

After the user selects “make,” the “run” command accesses the Freescale USB tap development interface to download and begin execution of user code.

 

 

 

UBOOT and the Freescale Linux Board Support Package

 

UBOOT permits users to download files.

 

UBOOT is loaded into the RDB DDR memory then flashed into the RDB flash memory using commands described in Freescale application note AN3947. UBOOT is configured for NFS deployment in the process, which allows networking commands to be used for the download process.

 

Steps to prepare the Freescale Linux BSP (Board Support Package) include:

·        Download the appropriate BSP

·        Build the kernel

·        Modify the device tree files for the board rev.

·        Place kernel and device tree in a directory for downloading later.

 

Additional steps before downloading the Linux kernel include using the setenv command to configure the host.

 

Compiling and downloading 8313 RDB Software

 

After the Linux kernel is appropriately installed, users can compile C or C++ code using Codewarrior and appropirate RDB interface drivers, make the package, and then use the “run” command to download it to the RDB. The console makes use of a serial port for user input and feedback during program operation.

 

8313RDB Configuration File Contents

 

Here are the contents of the 8313RDB configuration file:

 

#setMMRBaseAddr 0xFF400000

writereg      MBAR   0xFF400000

 

# change internal MMR base from 0xff400000 (reset value) to 0xe0000000

writemem.l 0xff400000 0xe0000000 # IMMRBAR = 0xe0000000

 

#setMMRBaseAddr 0xe0000000

writereg      MBAR   0xe0000000

 

 

##############################################

# System Configuration - Local Access Windows

##############################################

 

# Local Bus Local Access Windows

#################################

# WINDOW 0 - NOR FLASH

writemem.l 0xe0000020 0xfe000000 # LBLAWBAR0  - begining at 0xfe000000

writemem.l 0xe0000024 0x80000018 # LBLAWAR0   - enable, size = 32MB

 

# WINDOW 1 - NAND Flash

writemem.l 0xe0000028 0xf8000000 # LBLAWBAR1  - begining at 0xf8000000

writemem.l 0xe000002c 0x80000018 # LBLAWAR1   - enable, size = 32MB

 

# WINDOW 2 - VSC7385

writemem.l 0xe0000030 0xf0000000 # LBLAWBAR2  - begining at 0xfc100000

writemem.l 0xe0000034 0x80000010 # LBLAWAR2   - enable, size = 128kB

 

# WINDOW 3 - Read Write Buffer

writemem.l 0xe0000038 0xfa000000 # LBLAWBAR3  - begining at 0xfa000000

writemem.l 0xe000003c 0x8000000e # LBLAWAR3   - enable, size = 32kB

 

# PCI Local Access Windows

#################################

# WINDOW 0

writemem.l 0xe0000060 0x80000000 # PCILAWBAR0 - begining at 0x80000000

writemem.l 0xe0000064 0x8000001c # PCILAWAR0  - enable, size = 512MB

 

# WINDOW 1

writemem.l 0xe0000068 0xa0000000 # PCILAWBAR1 - begining at 0xa0000000

writemem.l 0xe000006c 0x8000001c # PCILAWAR1  - enable, size = 512MB

 

# DDR Local Access Windows

#################################

# WINDOW 0 - 1st DDR SODIMM

writemem.l 0xe00000a0 0x00000000 # DDRLAWBAR0 - begining at 0x00000000

writemem.l 0xe00000a4 0x8000001a # DDRLAWAR0  - enable, size = 128MB

 

       #*********************************

       # DDR2 Controller Registers

       #*********************************

 

       #DDRCDR

       writemem.l 0xE0000128 0x73000002

 

       # DDR_SDRAM_CLK_CNTL

       # CLK_ADJST = b'010' ; 2 Clocks

        writemem.l 0xE0002130 0x02000000

 

       # CS0_BNDS

       # SA0 = b'000000000000'

       # EA0 = b'000000000111'

       writemem.l 0xE0002000 0x00000007 ;# 128MB

      

       # CS0_CONFIG

       # CS_0_EN = b'1'

       # AP_0_EN = b'1'

       # ODT_RD_CFG = b'0'

       # ODT_WR_CFG = b'1'

       # BA_BITS_CS_0 = b'00'

       # ROW_BITS_CS_0 = b'001' ; 13 row bits

       # COL_BITS_CS_0 = b'010' ; 10 columns bits

       writemem.l 0xE0002080 0x80840102

 

       # TIMING_CFG_3

       # EXT_REFREC = b'000' ; 0 Clocks

       writemem.l 0xE0002100 0x00000000

      

 

       # TIMING_CONFIG_1

       # bit 1-3 = 2 - PRETOACT precharge activate interval 2 clock cycles

       # bit 4-7 = 6 - ACTTOPRE activate to precharge interval 6 clock cycles

       # bit 9-11 = 2 = ACTTORW activate to r/w interval 2 clock cycles

       # bit 13 - 15 = 5 - CASLAT CAS latency 3 clock cycles

       # bit 16 - 19 = 6 - REFREC refresh recovery time 14 clock cycles

       # bit 21 - 23 = 2 - WRREC data to precharge interval 2 clock cycles

       # bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles

       # bit 29 - 31 = 2 - WRTORD write data to read command interval 2 clock cycles

       writemem.l 0xe0002108 0x26256222

 

       # TIMING_CONFIG_2

       # bit 19-21  = b010  - WR_DATA_DELAY - 1/2 DRAM clock delay

       writemem.l 0xe000210C 0x0f9028c7

 

 

      

       # TIMING_CFG_0

       # RWT = b'00' ; 0 Clocks

       # WRT = b'00' ; 0 Clocks

       # RRT = b'00' ; 0 Clocks

       # WWT = b'00' ; 0 Clocks

       # ACT_PD_EXIT = b'010' ; 2 Clocks

       # PRE_PD_EXIT = b'010' ; 2 Clocks

       # ODT_PD_EXIT = b'1000' ; 8 Clocks

       # MRS_CYC = b'0010' ; 2 Clocks

       writemem.l 0xE0002104 0x00220802

 

       # DDR_SDRAM_CFG

       # MEM_EN = b'0'

       # SREN = b'1'

       # RD_EN = b'0'

       # SDRAM_TYPE = b'011'

       # DYN_PWR = b'0'

       # 32_BE = b'1'

       # 8_BE = b'0'

       # NCAP = b'0'

       # 2T_EN = b'0'

       # x32_EN = b'0'

       # PCHB8 = b'0'

       # HSE = b'0'

       # MEM_HALT = b'0'

       # BI = b'0'

       writemem.l 0xE0002110 0x43080000

      

       # DDR_SDRAM_CFG_2

       # FRC_SR = b'0'

       # DQS_CFG = b'00'

       # ODT_CFG = b'10'

       # NUM_PR = b'0001'

       # D_INIT = b'0'

       writemem.l 0xE0002114 0x00401000

 

       # DDR_SDRAM_MODE

       # Extended Mode Register: Outputs=0 or 1?

       # Mode Register

       writemem.l 0xE0002118 0x44400232

      

       # DDR_SDRAM_MODE_2

       # Extended Mode Register 2

       # Extended Mode Register 3

       writemem.l 0xE000211C 0x8000c000

             

       # DDR_SDRAM_INTERVAL

       # REFINT = 800 Clocks

       # BSTOPRE = 100 Clocks

       writemem.l 0xE0002124 0x03200064

      

       #delay before enable

       sleep 300

       #Enable: DDR_SDRAM_CFG

       writemem.l 0xE0002110 0xc3080000

 

 

##############################################

# Local Bus Interface (LBIU) Configuration

##############################################

 

# CS0 - 8MB NOR FLASH

writemem.l 0xe0005000 0xfe001001 # BR0 base address at 0xFE000000, port size 16 bit, GPCM, valid

writemem.l 0xe0005004 0xfe006ff7 # OR0 8MB flash size, 15 w.s., timing relaxed

 

# CS1 - NAND FLASH     

writemem.l    0xE0005008    0xF8000C21 # BR1 base address at 0xF8000000, port size 8 bit, FCM, valid

writemem.l    0xE000500c    0xFFFF83CC # OR1 32KB flash size, small page

#for a Rev A board, please comment the line above and use the below initialization for OR1:

#writemem.l   0xE000500c    0xFFFF93CC # OR1 32KB flash size, small page

 

# CS2 - VSC7385

writemem.l 0xe0005010 0xf0000801 # BR2 base address at 0xF0000000, port size 8 bit, GPCM, valid

writemem.l 0xe0005014 0xFFFE09FF # OR2 128KB

 

# CS3 - Read Write Buffer

writemem.l 0xe0005018 0xfa000801 # BR3 base address at 0xfa000000, port size 8 bit, GPCM, valid

writemem.l 0xe000501c 0xFFFF8FF7 # OR3 32KB

 

# LBCR - local bus enable

writemem.l 0xe00050d0 0x00000000

 

# LCRR

# bit 14 - 15 = 0b11 - EADC - 3 external address delay cycles

# bit 28 - 31 = 0x0010  - CLKDIV - system clock:memory bus clock = 2

writemem.l 0xe00050d4 0x00030002

 

 

writereg MSR 0x2000 # FP available, machine check disable, exception vectors at 0x0000_0000

 

writemem.l 0xE0000800 0x00000000 # ACR - Enable Core

 

 

writemem.l 0xfa000000 0x00000000 # write board LEDs

 

#

# NAND Flash settings

#

writemem.l    0xE00050E0    0x0000E000 # FMR

 

 

# MRTPR - refresh timer prescaler

writemem.l 0xe0005084 0x20000000

 

 

 

writereg SP 0xf